1. Field of the Invention
The present invention relates to an inductive element or inductor and more particularly, to an inductor structure formed on an insulating substructure and circuits incorporating such a structure.
2. Discussion of the Background Art
Planar-type inductors formed over a semiconductor substrate are frequently employed in integrated circuits designed for the millimeter and radio frequency band. As shown in FIG. 1, a planar-type inductor structure (8) typically has a spiral configuration which includes a ribbon or spiral of conductive metal (10) formed over a semiconductor substrate (12) through an insulating layer 14 on the substrate. The inductance value of the conventional square shaped inductor shown in FIG. 1 can be expressed as the following equation:                     L        =                              0.27            ⁢                                          (                d                )                                            8                /                3                                                                                        p                                  5                  /                  3                                            ⁡                              (                                  1                  +                                      1                    /                    r                                                  )                                                    5              /              3                                                          (        1        )            
Where L is the inductance (nH), d is a length (mm) of the most outer dimension of the spiral shaped inductor metalization layer (10), p is a width (mm) of the spiral-shaped inductor metalization layer 10, q is the spacing (mm) between two neighboring regions of the spiral-shaped metalization layer 10, and r is ratio of p/q, i.e. (p/q). When p=q, the above equation is simplified to the following equation:                     L        =                              0.085            ⁢                                          (                d                )                                            8                /                3                                                          p                          5              /              3                                                          (        2        )            
For example, if p=q=0.05 mm and d=0.5 mm, the inductance L is calculated from the above equation (1) or (2) as approximately 2 nH.
A principal advantage of the planar inductor construction described above is that it increases the level of integration for the circuit by reducing the number of circuit elements located off the chip along with attendant need for complex interconnections. Recently, however, to decrease the size and fabrication cost of semiconductor integrated circuit devices, not only active components (e.g., transistors) but also passive components (e.g., inductors and capacitors) have been required to be miniaturized more and more. The need for miniaturization in such devices as the inductor, however, has not relaxed the requirement to deliver the same or even higher values of inductance. Accordingly, for the above planar-type inductors, attempts have been made to address the miniaturization requirement by decreasing the size of the spiral-shaped conductor layer 10. That is, by reducing the size of the width p and the interval q.
For example, if p=0.006 mm, q=0.006 mm and d=0.15 mm, the inductance L is calculated from the above equation (1) to be approximately 2.5 nH. If the spiral-shaped metalization layer or conductor 10 having this dimension is formed on a GaAs substrate, the inter-line capacitance C of the conductor 10 is equal to approximately 0.06 pF. This value is obtained by an approximation of regarding the two neighboring regions of the spiral-shaped conductor (10) as coplanar strip lines. The resonance frequency fo in this case is approximately equal to 12.5 GHz, where fo is defined as the following equation (3):
fo=1/[2xcfx80(LC)xc2xd]xe2x80x83xe2x80x83(3)
To reduce the plan size of the spiral-shaped inductor metalization or conductor 10 to, say, 70% of its original size, if the above parameters are designed as p=0.0024 mm and q=0.001 mm, the inductance L can be maintained at approximately 2.5 nH. However, the inter-line capacitance C of the conductor 10 increases up to approximately 0.28 pF and, as a result, the resonance frequency fo will decrease to approximately 6.0 GHz, which is lower than the case of the original size by approximately 6.5 GHz. Accordingly, with the conventional inductor shown in FIG. 1, when the interval q of the neighboring regions of the spiral-shaped conductor 10 is decreased for miniaturization, the inter-line capacitance C will increase and the resonance frequency fo will decrease and, consequently, the maximum operable frequency is lowered.
In recognition of the practical constraints imposed on the maximum value of inductance which can be realized by a conventional planar inductor of the type shown in FIG. 1, it has been proposed to fabricate a multi-layer inductor component. One known multilayer inductor configuration is illustrated in FIG. 2. As seen in FIG. 2, the multilayer inductor structure 20 is fabricated with first and second levels of metalization constituting respective spiral inductor sections 22 and 24. Each of inductor sections 22 and 24 is formed on a corresponding insulating layer, designated generally at 26 and 28, respectively, and are connected end to end by a centrally locating conductive via 30. In comparison to the planar structure depicted in FIG. 1, the multilayer arrangement of FIG. 2 does provide a substantial increase in inductance per unit area, as well as a reduction in the dimension d.
Disadvantageously, however, employment of an end to end manner of interconnection in the structure of FIG. 2 means that the overall capacitance (end to end) has a negative effect on the self-resonance frequency. As such, the operating frequency range is still too limited for many new applications. In the exemplary prior art structure depicted in FIG. 2, where p=0.006 mm and q=0.006 mm and the overall dimension d was 0.105 mm, an inductance of 2.5 nH was obtained with a resonant frequency fo of 3.8 GHz and an inter-line capacitance of 0.046 pF.
Accordingly, there exists a need to provide an inductor arrangement for use in integrated circuits which is not only substantially more compact but which also operates at a substantially higher frequency than has heretofore been possible practicable.
The aforementioned need is addressed, and an advance is made in the art, by a multiple layer inductor structure in which the difference in phase current between upper and lower spiral inductor segments is reduced so as to thereby obtain not only a significant reduction in area but also a substantial increase in self-resonance frequency. In accordance with an illustrative embodiment of the present invention, the structure incorporates upper and lower spiral inductor sectionsxe2x80x94the lower section being disposed on the surface of a semiconductor substrate and the upper section being disposed on the surface of a dielectric layer which separates the respective spiral inductor sections.
A plurality of electrically conductive links or vias interconnect adjacent concentric segments of the spiral inductor sections. Accordingly, as current flows through the inductor element it passes from one of the upper and the lower inductor sections to the other of the upper and lower inductor sections, alternating between these levels a number of times (i.e., a number less than or equal to the number of concentric segments). Because current flows in the same direction in each of the upper and lower inductor sections, rather than in opposite directions, the mutual inductance between the upper and lower inductor sections has a net positive effect on the total value of inductance of the structure, rather than a negative effect.